This invention relates to a DC level clamping circuit.
As shown in FIG. 1, a conventional DC level clamping circuit includes an amplifier 1 and a series circuit of a capacitor 2 and a resistor 3. Through the capacitor 2 and the resistor 3 an output signal of a signal source 4 is supplied to the input terminal of the amplifier 1. The input terminal of the amplifier 1 is coupled to a DC power source 5 through a switch 6. Were the input impedance of the amplifier 1 infinitely large, a leak current would never flow through the amplifier 1, and the clamp voltage on the input terminal of the amplifier 1 would therefore remain constant all the time the switch 6 open.
In practice, however, the input impendance of the amplifier 1 has a finite value. A leak current inevitably flows through the amplifier 1 while the switch 6 remains open. As a result, the clamp voltage will be reduced gradually to cause a so-called "sag phenomenon", and the output voltage of the amplifier 1 will contain a sag component. To suppress such a sag phenomenon, a capacitor of large capacity may be used. But, if the capacitor 2 is formed to have a large capacitance, the transient characteristic of input voltage of the amplifier 1 at the turn-on of the switch 6 inevitably becomes too gentle. This transient characteristics of the input voltage depends on the time constant determined by the capacitance of the capacitor 2 and the resistance in the switch 6 in the turn-on state. Thus, to improve the transient characteristic of the input voltage, it is enough to reduce the resistance of the switch 6 at the turn-on. To achieve this objective, it is necessary that the switch 6 be constituted by a relatively large transistor and that the DC power source 5 have a large current capacity.